diff options
author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2019-05-23 11:52:44 +0800 |
---|---|---|
committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-06-20 10:44:09 +0530 |
commit | 2b12f6cfe6239d8b6b8c5e7b0c5b5851f7bc489a (patch) | |
tree | 6d0ebb01974bb833c5a5be3f379919e7256259f1 /arch/powerpc/cpu | |
parent | c16dfd016afb92771d425ae84a2949da1d7e112b (diff) |
powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to Kconfig
Use the Kconfig option to select the PCIe reset errata.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/powerpc/cpu')
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 6c3c164883..7572404625 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -533,6 +533,7 @@ config ARCH_BSC9132 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_I2C_A004447 select SYS_FSL_ERRATUM_IFC_A002769 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -551,6 +552,7 @@ config ARCH_C29X select SYS_FSL_DDR_VER_46 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -566,6 +568,7 @@ config ARCH_MPC8536 select FSL_LAW select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -594,6 +597,7 @@ config ARCH_MPC8544 bool select FSL_LAW select SYS_FSL_ERRATUM_A005125 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -609,6 +613,7 @@ config ARCH_MPC8548 select SYS_FSL_ERRATUM_NMG_LBC103 select SYS_FSL_ERRATUM_NMG_ETSEC129 select SYS_FSL_ERRATUM_I2C_A004447 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR1 select SYS_FSL_HAS_SEC @@ -633,6 +638,7 @@ config ARCH_MPC8560 config ARCH_MPC8568 bool select FSL_LAW + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -643,6 +649,7 @@ config ARCH_MPC8569 select FSL_LAW select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -657,6 +664,7 @@ config ARCH_MPC8572 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_DDR_115 select SYS_FSL_ERRATUM_DDR111_DDR134 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -681,6 +689,7 @@ config ARCH_P1010 select SYS_FSL_ERRATUM_P1010_A003549 select SYS_FSL_ERRATUM_SEC_A003571 select SYS_FSL_ERRATUM_IFC_A003399 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -718,6 +727,7 @@ config ARCH_P1020 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -738,6 +748,7 @@ config ARCH_P1021 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -759,6 +770,7 @@ config ARCH_P1022 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_SATA_A001 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -772,6 +784,7 @@ config ARCH_P1023 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_I2C_A004447 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -786,6 +799,7 @@ config ARCH_P1024 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -807,6 +821,7 @@ config ARCH_P1025 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -824,6 +839,7 @@ config ARCH_P2020 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_ESDHC_A001 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -1079,6 +1095,7 @@ config ARCH_T2080 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 @@ -1101,6 +1118,7 @@ config ARCH_T2081 select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 @@ -1437,6 +1455,9 @@ config SYS_P4080_ERRATUM_SERDES_A005 config FSL_PCIE_DISABLE_ASPM bool +config FSL_PCIE_RESET + bool + config SYS_FSL_QORIQ_CHASSIS1 bool |