diff options
| author | Dave Liu <daveliu@freescale.com> | 2009-12-08 11:56:48 +0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-04-26 22:37:53 -0500 |
| commit | 99bac479dd183529f4e259a0de8d31644219d487 (patch) | |
| tree | 2ccdc234baf44fc4dc11c4726b73d8e9e0e9189d /arch/powerpc/cpu | |
| parent | f8d05e5e5888d88ab42524d699924936e8e77970 (diff) | |
fsl-ddr: Add extra cycle to turnaround times
Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 03f9c4380d..4a282bc52d 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -198,6 +198,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) pre_pd_exit_mclk = act_pd_exit_mclk; taxpd_mclk = 8; tmrd_mclk = 4; + /* set the turnaround time */ + trwt_mclk = 1; #else /* CONFIG_FSL_DDR2 */ /* * (tXARD and tXARDS). Empirical? |