diff options
| author | Joakim Tjernlund <joakim.tjernlund@infinera.com> | 2019-11-27 19:35:10 +0100 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2019-12-23 14:07:55 +0530 |
| commit | 2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee (patch) | |
| tree | 251f9fa102648ac6c3167aa1a0694cbdd4a6b97c /arch/powerpc/dts/mpc8548cds_36b.dts | |
| parent | 71094b72d7113cbb2c566eac43fc122a18e5c6f9 (diff) | |
mpc85xx: ddr: Always start DDR RAM in Self Refresh mode
Some of t1042 boards fails DDR init with an Automatic calibration error
every now and then. Investigations revealed that true Warm boots
never failed. Warm boots has some extra steps performed, one being
to start DDRC in Self Refresh and then clearing SR right after.
Applying this SR method unconditionally made all our boards
stable again, regardless of Cold/Warm boot.
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/powerpc/dts/mpc8548cds_36b.dts')
0 files changed, 0 insertions, 0 deletions