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authorTom Rini <trini@konsulko.com>2019-08-29 07:26:13 -0400
committerTom Rini <trini@konsulko.com>2019-08-29 07:26:13 -0400
commit25f32e0dffb17292dc17cd0f6694dd5e91c405a2 (patch)
tree72f737787a843f1609168e7120cea424ac937b2c /arch/powerpc/dts/p1020rdb-pd.dts
parent80505e59df9bddc9037bd2145b0fff38f4a0d95e (diff)
parent43e881e38b505835dd3d20ab35b5845bc20a1aae (diff)
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
Enable DM PCI for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, and MPC8548CDS
Diffstat (limited to 'arch/powerpc/dts/p1020rdb-pd.dts')
-rw-r--r--arch/powerpc/dts/p1020rdb-pd.dts12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 81f25a3866..21174a09be 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -18,6 +18,18 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
/include/ "p1020-post.dtsi"