diff options
| author | Tom Rini <trini@konsulko.com> | 2019-08-29 07:26:13 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-08-29 07:26:13 -0400 |
| commit | 25f32e0dffb17292dc17cd0f6694dd5e91c405a2 (patch) | |
| tree | 72f737787a843f1609168e7120cea424ac937b2c /arch/powerpc/dts/t102x.dtsi | |
| parent | 80505e59df9bddc9037bd2145b0fff38f4a0d95e (diff) | |
| parent | 43e881e38b505835dd3d20ab35b5845bc20a1aae (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
Enable DM PCI for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB,
P2020RDB, P2041RDB, P3041DS, P4080DS, and MPC8548CDS
Diffstat (limited to 'arch/powerpc/dts/t102x.dtsi')
| -rw-r--r-- | arch/powerpc/dts/t102x.dtsi | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi index 2393e316f8..c49fd21088 100644 --- a/arch/powerpc/dts/t102x.dtsi +++ b/arch/powerpc/dts/t102x.dtsi @@ -49,4 +49,40 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; }; |