diff options
author | Jagdish Gediya <jagdish.gediya@nxp.com> | 2018-09-03 21:35:12 +0530 |
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committer | York Sun <york.sun@nxp.com> | 2018-09-27 10:14:14 -0700 |
commit | 432054b947a79dbf0f1554f6d6814e8ea8ecb623 (patch) | |
tree | d87f6d5f0c07b33d02469026e66ea92211b3b471 /arch/powerpc/dts/t2080.dtsi | |
parent | 3a2f59e244bcd7f959686eeb931f1acb6f86628d (diff) |
powerpc: dts: Enable device tree support for T2080QDS
Add device tree for T2080QDS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/dts/t2080.dtsi')
-rw-r--r-- | arch/powerpc/dts/t2080.dtsi | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi new file mode 100644 index 0000000000..db65ea5725 --- /dev/null +++ b/arch/powerpc/dts/t2080.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T2080/T2081 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2018 NXP + */ + +/dts-v1/; + +/include/ "e6500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e6500@0 { + device_type = "cpu"; + reg = <0 1>; + fsl,portid-mapping = <0x80000000>; + }; + cpu1: PowerPC,e6500@2 { + device_type = "cpu"; + reg = <2 3>; + fsl,portid-mapping = <0x80000000>; + }; + cpu2: PowerPC,e6500@4 { + device_type = "cpu"; + reg = <4 5>; + fsl,portid-mapping = <0x80000000>; + }; + cpu3: PowerPC,e6500@6 { + device_type = "cpu"; + reg = <6 7>; + fsl,portid-mapping = <0x80000000>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; +}; |