diff options
| author | Yinbo Zhu <yinbo.zhu@nxp.com> | 2019-10-15 17:20:41 +0800 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2019-11-25 11:54:26 +0530 |
| commit | e126363dc7cce3c8655a4eb942494500c302baad (patch) | |
| tree | 06507fec08dd1c1120e87b49777d75126e189fa2 /arch/powerpc/dts | |
| parent | b73d5379c534f5419c60e9d10c200972ad627f10 (diff) | |
arch: powerpc: add eSDHC node to p2020 dts
Add eSDHC node to p2020 dts
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/powerpc/dts')
| -rw-r--r-- | arch/powerpc/dts/p2020-post.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index f696f35960..c07ed66726 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -24,6 +24,13 @@ single-cpu-affinity; last-interrupt-source = <255>; }; + + esdhc: esdhc@2e000 { + compatible = "fsl,esdhc"; + reg = <0x2e000 0x1000>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; }; /* PCIe controller base address 0x8000 */ |