diff options
| author | Zang Roy-R61911 <tie-fei.zang@freescale.com> | 2013-07-04 07:25:03 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:41 -0700 |
| commit | 7b4e58440f7813a952133e77f2d9c4a475730e40 (patch) | |
| tree | 9d2082e2063031e51b07ea1f040d35c3263accb0 /arch/powerpc/include/asm/config_mpc85xx.h | |
| parent | 0795eff34c5744dcc59ead6edbbcd2cd600f58fe (diff) | |
powerpc/pcie: add PCIe version 3.x support
T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.
1. Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.
2. add the status/control register define
use status/control register to judge the link status
3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.
This patch fixes the PCIe card link up issue on T4240QDS.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/config_mpc85xx.h')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index f946389695..517e9b29de 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -578,6 +578,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_PCI_VER_3_X #ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 |