diff options
| author | York Sun <york.sun@nxp.com> | 2016-12-28 08:43:40 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-01-04 19:40:41 -0500 |
| commit | d26e34c4c4b6473fdbd412a3b2dc33a94b08e8ff (patch) | |
| tree | 22eaf9594d9a0b0dbbe31a489a7a80f751939b1a /arch/powerpc/include/asm/config_mpc85xx.h | |
| parent | a10550385169e456950add6f3e2a4774d6aea67c (diff) | |
fsl_ddr: Move DDR config options to driver Kconfig
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/powerpc/include/asm/config_mpc85xx.h')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4e9fcc84fe..6aee5bcca1 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -16,7 +16,6 @@ #define CONFIG_PPC_SPINTABLE_COMPATIBLE #include <fsl_ddrc_version.h> -#define CONFIG_SYS_FSL_DDR_BE /* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE @@ -28,17 +27,13 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_MPC8540) -#define CONFIG_SYS_FSL_DDRC_GEN1 #elif defined(CONFIG_ARCH_MPC8541) -#define CONFIG_SYS_FSL_DDRC_GEN1 #elif defined(CONFIG_ARCH_MPC8544) -#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_MPC8548) -#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 @@ -52,13 +47,10 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 #elif defined(CONFIG_ARCH_MPC8555) -#define CONFIG_SYS_FSL_DDRC_GEN1 #elif defined(CONFIG_ARCH_MPC8560) -#define CONFIG_SYS_FSL_DDRC_GEN1 #elif defined(CONFIG_ARCH_MPC8568) -#define CONFIG_SYS_FSL_DDRC_GEN2 #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 @@ -544,9 +536,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ -#ifdef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDRC_GEN4 -#endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 @@ -588,9 +577,6 @@ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_SYS_FMAN_V3 -#ifdef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDRC_GEN4 -#endif #define CONFIG_SYS_FSL_NUM_CC_PLL 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 @@ -697,13 +683,6 @@ #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 #endif -#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ - !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ - !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ - !defined(CONFIG_SYS_FSL_DDRC_GEN4) -#define CONFIG_SYS_FSL_DDRC_GEN3 -#endif - #if !defined(CONFIG_ARCH_C29X) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #endif |