diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2018-10-08 06:55:57 -0700 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2018-10-29 13:19:43 -0700 |
| commit | db148f2a6938b47cf26c5fd11481e7462a6a793a (patch) | |
| tree | 1655d16c3f0cf0fed46024b5c4596da17ab8dfc6 /arch/powerpc/include/asm/immap_85xx.h | |
| parent | c00d0012f5d6aa3987f5465caf8b6ead5ac919ff (diff) | |
powerpc: t1040: Correct RCW EC2 settings
Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2
settings.
- The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should
be 0x04000000 (value of 1 in RCW bit [420:421])
- Value of 2/3 are reserved in RCW bit [420:421], hence there is no
macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/include/asm/immap_85xx.h')
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 8ec2a38aad..bfa601e91b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1785,8 +1785,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */ #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 -#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 -#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080 |