diff options
| author | Aneesh Bansal <aneesh.bansal@nxp.com> | 2016-01-22 16:37:25 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-01-27 08:12:42 -0800 |
| commit | 0a6b2714adfffce6a1497bd2ed6cbf4f7b4b0236 (patch) | |
| tree | 4fdce7b3d54b46c4e66997dac5267391b4a0713c /arch/powerpc/include/asm | |
| parent | bdc22074c511def222f93d1a9d94ec95c462c062 (diff) | |
secure_boot: create function to determine boot mode
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 101b8db0ee..fd8aba42a5 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1749,6 +1749,8 @@ typedef struct ccsr_gur { u32 brrl; /* Boot release */ u8 res17[24]; u32 rcwsr[16]; /* Reset control word status */ +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 @@ -2194,6 +2196,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 #endif +#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000 /* The 8544 RM says this is bit 26, but it's really bit 24 */ #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 u8 res1[8]; |