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authorYork Sun <yorksun@freescale.com>2012-10-28 08:12:54 +0000
committerAndy Fleming <afleming@freescale.com>2012-11-27 18:28:06 -0600
commit2a5fcb835f6e976ed0eb34c413d40f2d4a5e8d1f (patch)
treebfb0622c88026a5b3e7f7153bd1a90873001394b /arch/powerpc/include
parentca1b0b89568cecaf2ecdbcbef714722d70021094 (diff)
powerpc/mpc85xx: Temporary fix for spin table backward compatibility
Once u-boot sets the spin table to cache-enabled memory, old kernel which uses cache-inhibit mapping without coherence will not work properly. We use this temporary fix until kernel has updated its spin table code. For now this fix is activated by default. To disable this fix for new kernel, set environmental variable "spin_table_compat=no". After kernel has updated spin table code, this default shall be changed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 61dd061427..d1c1e0681a 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -27,6 +27,12 @@
#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
#endif
+/*
+ * This macro should be removed when we no longer care about backwards
+ * compatibility with older operating systems.
+ */
+#define CONFIG_PPC_SPINTABLE_COMPATIBLE
+
#define FSL_DDR_VER_4_7 47
/* Number of TLB CAM entries we have on FSL Book-E chips */