ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration

The four x16 DDR3 are wired in T-topology. From NXP AN4467:
'Although not required, T-Topologies may also benefit from performing
Write Leveling as there are package delays on both the processor and DDR
devices that can be de-skewed by performing Write Leveling. Therefore,
Freescale recommends determining Write Leveling calibration parameters
for all boards, regardless of topology used.'
That is why write level calibration is also done.

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>

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