diff options
| author | Roy Zang <tie-fei.zang@freescale.com> | 2011-01-07 00:06:47 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-01-14 01:32:22 -0600 |
| commit | 3b4456ec391877a950dd5e98ee20df6560f0e1af (patch) | |
| tree | 1690d31ee59b2bbc8e6d5db326aac3c06bc43a6b /arch/powerpc | |
| parent | d621da0066dff92a76ca3c6fb031a7f823a811f3 (diff) | |
fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)
The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.
Clear these bits out when we read HOSTCAPBLT.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 0c4820c089..d5c34c867f 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -53,6 +53,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) puts("Work-around for Erratum ESDHC111 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) + puts("Work-around for Erratum ESDHC135 enabled\n"); +#endif return 0; } |