diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2012-04-29 23:57:25 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-07-06 17:30:31 -0500 |
| commit | e87dc41fc11189fd51b2954e444ae8cc0ed50eba (patch) | |
| tree | 1ff8ab0f61ac286a1320d032790e944ff4963a48 /arch/powerpc | |
| parent | ad75d44239e3d57bb1bf4607a0e5d075f4a73a27 (diff) | |
powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting
During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.
Avoid updating these register.They will be programmed during NAND RAMBOOT.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index f33db021f1..bf7a6f6be6 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -26,32 +26,6 @@ void cpu_init_f(void) { -#ifdef CONFIG_FSL_LBC - fsl_lbc_t *lbc = LBC_BASE_ADDR; - - /* - * LCRR - Clock Ratio Register - set up local bus timing - * when needed - */ - out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); - -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); -#else -#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined -#endif -#endif -#ifdef CONFIG_FSL_IFC -#ifndef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); -#endif -#endif -#endif - #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; |