diff options
| author | Rick Chen <rick@andestech.com> | 2019-04-02 15:56:39 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-04-08 09:45:08 +0800 |
| commit | 0d389468e2144f3ba3bdbc566c05c0c05dc14fc6 (patch) | |
| tree | b48b25b552a66db5d7e92dd23bdacf82484ddd41 /arch/riscv/Kconfig | |
| parent | d0a8fd3e4d2a5ab19b8f2d27d40dacb4942ba5a4 (diff) | |
riscv: Add a SYSCON driver for Andestech's PLIC
The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3a4470daf3..511768befc 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -109,6 +109,15 @@ config SIFIVE_CLINT The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config ANDES_PLIC + bool + depends on RISCV_MMODE + select REGMAP + select SYSCON + help + The Andes PLIC block holds memory-mapped claim and pending registers + associated with software interrupt. + config RISCV_RDTIME bool default y if RISCV_SMODE |