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authorTom Rini <trini@konsulko.com>2019-12-09 21:53:23 -0500
committerTom Rini <trini@konsulko.com>2019-12-09 21:53:23 -0500
commit520f9559020894950d4e962aba52220c8a1d6bfe (patch)
treef39b28ef809b2cd4236803e9e1d7f98c97f0dbd5 /arch/riscv/cpu/ax25/Kconfig
parent1045ff4d1af9e3e8a2ad4cf04a7263d49e90cfa7 (diff)
parent0e1233ce9069a87a84a4385de456665d2bc9229d (diff)
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Increase stack size to avoid a stack overflow during distro boot. - Add hifive-unleashed-a00.dts for SIFIVE FU540. - Add OF_SEPARATE support for SIFIVE FU540. - Add SPL support for Andes AX25 AE350. - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
Diffstat (limited to 'arch/riscv/cpu/ax25/Kconfig')
-rw-r--r--arch/riscv/cpu/ax25/Kconfig4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index d411a79c21..8d8d71dcbf 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -6,7 +6,9 @@ config RISCV_NDS
imply RISCV_TIMER
imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
- imply V5L2_CACHE
+ imply SPL_CPU_SUPPORT
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
help
Run U-Boot on AndeStar V5 platforms and use some specific features
which are provided by Andes Technology AndeStar V5 families.