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| author | Tom Rini <trini@konsulko.com> | 2019-09-02 23:21:44 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-09-02 23:21:44 -0400 |
| commit | 83a5df42614c566c3c642871f683e66a53d228ae (patch) | |
| tree | ea53c8fd1dd9bf65bc1d29dd9a0957d060dc1917 /arch/riscv/cpu/ax25/Kconfig | |
| parent | d22c8be964a870f59d2fdab6c67cefa0c4799364 (diff) | |
| parent | 61ce84b2cf1a6672c8e402ce8174554b25629692 (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Skip unavailable hart in the get_count().
- fu540 set serial env from otp.
- fu540 add mmc0 as a boot target device.
- Update fix_rela_dyn and add absolute reloc addend.
- Andestech PLIC driver will skip unavailable hart.
- Support Andestech V5L2 cache driver.
Diffstat (limited to 'arch/riscv/cpu/ax25/Kconfig')
| -rw-r--r-- | arch/riscv/cpu/ax25/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index f4b59cb71d..d411a79c21 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -6,6 +6,7 @@ config RISCV_NDS imply RISCV_TIMER imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) + imply V5L2_CACHE help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. |