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authorBin Meng <bmeng.cn@gmail.com>2018-12-12 06:12:38 -0800
committerAndes <uboot@andestech.com>2018-12-18 09:56:27 +0800
commitaef59e5cc450f403478f799bbb0f0647ff28a3c3 (patch)
treea8dd18c0e493e9614a4e7331dd832d945ad963de /arch/riscv/cpu
parent3967156464282df161f5e4be40999dae47adf799 (diff)
riscv: Update supports_extension() to use desc from cpu driver
This updates supports_extension() implementation to use the desc string from the cpu driver whenever possible, which avoids the reading of misa CSR for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/cpu')
-rw-r--r--arch/riscv/cpu/cpu.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index d3c59da34b..fc7c9b3751 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -5,8 +5,10 @@
#include <common.h>
#include <cpu.h>
+#include <dm.h>
#include <log.h>
#include <asm/csr.h>
+#include <dm/uclass-internal.h>
/*
* prior_stage_fdt_address must be stored in the data section since it is used
@@ -16,7 +18,31 @@ phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
static inline bool supports_extension(char ext)
{
+#ifdef CONFIG_CPU
+ struct udevice *dev;
+ char desc[32];
+
+ uclass_find_first_device(UCLASS_CPU, &dev);
+ if (!dev) {
+ debug("unable to find the RISC-V cpu device\n");
+ return false;
+ }
+ if (!cpu_get_desc(dev, desc, sizeof(desc))) {
+ /* skip the first 4 characters (rv32|rv64) */
+ if (strchr(desc + 4, ext))
+ return true;
+ }
+
+ return false;
+#else /* !CONFIG_CPU */
+#ifdef CONFIG_RISCV_MMODE
return csr_read(misa) & (1 << (ext - 'a'));
+#else /* !CONFIG_RISCV_MMODE */
+#warning "There is no way to determine the available extensions in S-mode."
+#warning "Please convert your board to use the RISC-V CPU driver."
+ return false;
+#endif /* CONFIG_RISCV_MMODE */
+#endif /* CONFIG_CPU */
}
static int riscv_cpu_probe(void)