diff options
| author | Rick Chen <rick@andestech.com> | 2019-04-30 13:49:33 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-05-09 16:46:46 +0800 |
| commit | bdce38965e79143ed58bf1c6d39c650ff3dfefd1 (patch) | |
| tree | dfb6c4288f22c176838ace87fed0949dd747a7dc /arch/riscv/cpu | |
| parent | 8aa278df0a338dfc05c731589051ab80373925c5 (diff) | |
riscv: Introduce CONFIG_XIP to support booting from flash
When U-Boot boots from flash, during the boot process,
hart_lottery and available_harts_lock variable addresses
point to flash which is not writable. This causes boot
failures on AE350. Introduce a config option CONFIG_XIP
to support such configuration.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/cpu')
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 2 | ||||
| -rw-r--r-- | arch/riscv/cpu/start.S | 6 |
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c32de8a4c3..0cfd7d61a7 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -16,6 +16,7 @@ * before the bss section is available. */ phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; /* @@ -23,6 +24,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0; * finished initialization of global data. */ u32 available_harts_lock = 1; +#endif static inline bool supports_extension(char ext) { diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a4433fbd6b..3402d09a05 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -98,6 +98,7 @@ call_board_init_f_0: mv sp, a0 #endif +#ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts * wait for initialization to complete. @@ -106,6 +107,9 @@ call_board_init_f_0: li s2, 1 amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init +#else + bnez tp, secondary_hart_loop +#endif la t0, prior_stage_fdt_address SREG s1, 0(t0) @@ -115,6 +119,7 @@ call_board_init_f_0: /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp) +#ifndef CONFIG_XIP la t0, available_harts_lock fence rw, w amoswap.w zero, zero, 0(t0) @@ -141,6 +146,7 @@ wait_for_gd_init: * secondary_hart_loop. */ bnez s2, secondary_hart_loop +#endif /* Enable cache */ jal icache_enable |