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authorAnup Patel <Anup.Patel@wdc.com>2019-02-25 08:14:10 +0000
committerAndes <uboot@andestech.com>2019-02-27 09:12:33 +0800
commitfdff1f96a6505bccb258f5b52e6c94c7e0b29512 (patch)
tree158b092ab1119bcab415f46c91f5a5865db0ea1c /arch/riscv/include/asm
parent7c8d210b91a192e89be3bfc9c0e943422df108b0 (diff)
riscv: Rename cpu/qemu to cpu/generic
The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/include/asm')
0 files changed, 0 insertions, 0 deletions