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authorLukas Auer <lukas.auer@aisec.fraunhofer.de>2019-03-17 19:28:36 +0100
committerAndes <uboot@andestech.com>2019-04-08 09:44:26 +0800
commit1446b26f7652124f0e3e98c348cdbc4fc55eb0cb (patch)
tree58ef47a874006860056e4393224ac111ef25571d /arch/riscv/include
parent2503ccc55ff2031ae2ff476fb06f666e6d1c7a64 (diff)
riscv: save hart ID in register tp instead of s0
The hart ID passed by the previous boot stage is currently stored in register s0. If we divert the control flow inside a function, which is required as part of multi-hart support, the function epilog may not be called, clobbering register s0. Save the hart ID in the unallocatable register tp instead to protect the hart ID. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'arch/riscv/include')
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