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authorRick Chen <rick@andestech.com>2017-12-26 13:55:48 +0800
committerTom Rini <trini@konsulko.com>2018-01-12 08:05:12 -0500
commite8e39597a33cc53aacbaf4ef5cae60ed86d6a20a (patch)
treec31439c473ea9fce54ff32851bf2d3058acab33a /arch/riscv/lib/boot.c
parent373b9003410b44a1133060c2e63483b278fb476b (diff)
riscv: cpu: Add nx25 to support RISC-V
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok. Detail verification message please see doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
Diffstat (limited to 'arch/riscv/lib/boot.c')
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