diff options
| author | Rick Chen <rick@andestech.com> | 2019-11-14 13:52:24 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-12-10 08:23:10 +0800 |
| commit | 43a0832ba09068d1ab0628afbe62e498450ece63 (patch) | |
| tree | 788ce3e2f6e2c6761d87f889916ea43f17d904a4 /arch/riscv/lib | |
| parent | 7e24518c904d9cab8185a1248a24e86c4ceb19ae (diff) | |
riscv: andes_plic: Fix some wrong configurations
Fix two wrong settings of andes plic driver as below:
1. Fix wrong pending register base definition.
2. Declaring the en variable in enable_ipi() as unsigned int instead of
int can help to fix wrong plic enabling setting in RV64.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Diffstat (limited to 'arch/riscv/lib')
| -rw-r--r-- | arch/riscv/lib/andes_plic.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 28568e4e2b..42394b9b6e 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -19,7 +19,7 @@ #include <cpu.h> /* pending register */ -#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + (hart) * 8) +#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) /* enable register */ #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) /* claim register */ @@ -46,7 +46,7 @@ static int init_plic(void); static int enable_ipi(int hart) { - int en; + unsigned int en; en = ENABLE_HART_IPI >> hart; writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); @@ -94,10 +94,13 @@ static int init_plic(void) int riscv_send_ipi(int hart) { + unsigned int ipi; + PLIC_BASE_GET(); - writel(SEND_IPI_TO_HART(hart), - (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart)); + ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); + writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, + gd->arch.boot_hart)); return 0; } |