diff options
| author | Lukas Auer <lukas.auer@aisec.fraunhofer.de> | 2018-11-22 11:26:20 +0100 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-11-26 13:57:30 +0800 |
| commit | 5a441736b7dda7fd4dde0a2417aeab59a9ef9424 (patch) | |
| tree | 517937987353bdb4d40dcca11e56a5d14ba1f56e /arch/riscv | |
| parent | f105d2efcb086a7e05b75c04e26432d3d8995b9b (diff) | |
riscv: complete the list of exception codes
Only the first four exception codes are defined. Add the missing
exception codes from the definition in RISC-V Privileged Architecture
Version 1.10.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/lib/interrupts.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 62a16b4da9..6a12818c2b 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -67,7 +67,18 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) "Instruction access fault", "Illegal instruction", "Breakpoint", - "Load address misaligned" + "Load address misaligned", + "Load access fault", + "Store/AMO address misaligned", + "Store/AMO access fault", + "Environment call from U-mode", + "Environment call from S-mode", + "Reserved", + "Environment call from M-mode", + "Instruction page fault", + "Load page fault", + "Reserved", + "Store/AMO page fault", }; printf("exception code: %ld , %s , epc %lx , ra %lx\n", |