diff options
| author | Bin Meng <bin.meng@windriver.com> | 2020-06-08 20:28:26 -0700 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-07-02 10:03:03 +0800 |
| commit | 76585c9ecc987fb1747345c6ca27e5034e872b2c (patch) | |
| tree | a1cd4cff33035fa39640b8f833e6a5696a9f0726 /arch/riscv | |
| parent | 6c6a29cde4d962550c5ddca8e7b13e5d6262e2db (diff) | |
riscv: fu540: dts: Correct reg size of otp and dmc nodes
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 0d3f7108fa..35c153d851 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -50,7 +50,7 @@ u-boot,dm-spl; otp: otp@10070000 { compatible = "sifive,fu540-c000-otp"; - reg = <0x0 0x10070000 0x0 0x0FFF>; + reg = <0x0 0x10070000 0x0 0x1000>; fuse-count = <0x1000>; }; clint@2000000 { @@ -63,7 +63,7 @@ compatible = "sifive,fu540-c000-ddr"; reg = <0x0 0x100b0000 0x0 0x0800 0x0 0x100b2000 0x0 0x2000 - 0x0 0x100b8000 0x0 0x0fff>; + 0x0 0x100b8000 0x0 0x1000>; clocks = <&prci PRCI_CLK_DDRPLL>; clock-frequency = <933333324>; u-boot,dm-spl; |