diff options
| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2019-05-07 21:52:47 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-05-10 22:43:18 +0200 |
| commit | 7de3ea8b98a531c516505f07902e56077bf78816 (patch) | |
| tree | 2cc2816ddca0073fd77d29e812dccc9f9df3d972 /arch/sh/include/asm | |
| parent | 54eac8b3a3cc4c05d981ecefc8bcd5151f0d928c (diff) | |
sh: sh2: Remove CPU support
This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Diffstat (limited to 'arch/sh/include/asm')
| -rw-r--r-- | arch/sh/include/asm/config.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh2.h | 30 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh7203.h | 41 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh7264.h | 41 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh7269.h | 26 | ||||
| -rw-r--r-- | arch/sh/include/asm/processor.h | 4 |
6 files changed, 1 insertions, 143 deletions
diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h index d2862df4a5..df38c82abc 100644 --- a/arch/sh/include/asm/config.h +++ b/arch/sh/include/asm/config.h @@ -6,13 +6,11 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#if !defined(CONFIG_CPU_SH2) #include <asm/processor.h> /* Timer */ #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0x8) /* TCNT0 */ #define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4) -#endif #endif diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h deleted file mode 100644 index d98bedd625..0000000000 --- a/arch/sh/include/asm/cpu_sh2.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * Copyright (C) 2008 Renesas Solutions Corp. - */ - -#ifndef _ASM_CPU_SH2_H_ -#define _ASM_CPU_SH2_H_ - -/* cache control */ -#define CCR_CACHE_STOP 0x00000008 -#define CCR_CACHE_ENABLE 0x00000005 -#define CCR_CACHE_ICI 0x00000008 - -#define CACHE_OC_ADDRESS_ARRAY 0xf0000000 -#define CACHE_OC_WAY_SHIFT 13 -#define CACHE_OC_NUM_ENTRIES 256 -#define CACHE_OC_ENTRY_SHIFT 4 - -#if defined(CONFIG_CPU_SH7203) -# include <asm/cpu_sh7203.h> -#elif defined(CONFIG_CPU_SH7264) -# include <asm/cpu_sh7264.h> -#elif defined(CONFIG_CPU_SH7269) -# include <asm/cpu_sh7269.h> -#else -# error "Unknown SH2 variant" -#endif - -#endif /* _ASM_CPU_SH2_H_ */ diff --git a/arch/sh/include/asm/cpu_sh7203.h b/arch/sh/include/asm/cpu_sh7203.h deleted file mode 100644 index 77dcac43d3..0000000000 --- a/arch/sh/include/asm/cpu_sh7203.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _ASM_CPU_SH7203_H_ -#define _ASM_CPU_SH7203_H_ - -/* Cache */ -#define CCR1 0xFFFC1000 -#define CCR CCR1 - -/* PFC */ -#define PACR 0xA4050100 -#define PBCR 0xA4050102 -#define PCCR 0xA4050104 -#define PETCR 0xA4050106 - -/* Port Data Registers */ -#define PADR 0xA4050120 -#define PBDR 0xA4050122 -#define PCDR 0xA4050124 - -/* BSC */ - -/* SDRAM controller */ - -/* SCIF */ -#define SCSMR_0 0xFFFE8000 -#define SCIF0_BASE SCSMR_0 - -/* Timer(CMT) */ -#define CMSTR 0xFFFEC000 -#define CMCSR_0 0xFFFEC002 -#define CMCNT_0 0xFFFEC004 -#define CMCOR_0 0xFFFEC006 -#define CMCSR_1 0xFFFEC008 -#define CMCNT_1 0xFFFEC00A -#define CMCOR_1 0xFFFEC00C - -/* On chip oscillator circuits */ -#define FRQCR 0xA415FF80 -#define WTCNT 0xA415FF84 -#define WTCSR 0xA415FF86 - -#endif /* _ASM_CPU_SH7203_H_ */ diff --git a/arch/sh/include/asm/cpu_sh7264.h b/arch/sh/include/asm/cpu_sh7264.h deleted file mode 100644 index a4a4d51597..0000000000 --- a/arch/sh/include/asm/cpu_sh7264.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _ASM_CPU_SH7264_H_ -#define _ASM_CPU_SH7264_H_ - -/* Cache */ -#define CCR1 0xFFFC1000 -#define CCR CCR1 - -/* PFC */ -#define PACR 0xA4050100 -#define PBCR 0xA4050102 -#define PCCR 0xA4050104 -#define PETCR 0xA4050106 - -/* Port Data Registers */ -#define PADR 0xA4050120 -#define PBDR 0xA4050122 -#define PCDR 0xA4050124 - -/* BSC */ - -/* SDRAM controller */ - -/* SCIF */ -#define SCSMR_3 0xFFFE9800 -#define SCIF3_BASE SCSMR_3 - -/* Timer(CMT) */ -#define CMSTR 0xFFFEC000 -#define CMCSR_0 0xFFFEC002 -#define CMCNT_0 0xFFFEC004 -#define CMCOR_0 0xFFFEC006 -#define CMCSR_1 0xFFFEC008 -#define CMCNT_1 0xFFFEC00A -#define CMCOR_1 0xFFFEC00C - -/* On chip oscillator circuits */ -#define FRQCR 0xA415FF80 -#define WTCNT 0xA415FF84 -#define WTCSR 0xA415FF86 - -#endif /* _ASM_CPU_SH7264_H_ */ diff --git a/arch/sh/include/asm/cpu_sh7269.h b/arch/sh/include/asm/cpu_sh7269.h deleted file mode 100644 index 4dea7086d4..0000000000 --- a/arch/sh/include/asm/cpu_sh7269.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _ASM_CPU_SH7269_H_ -#define _ASM_CPU_SH7269_H_ - -/* Cache */ -#define CCR1 0xFFFC1000 -#define CCR CCR1 - -/* SCIF */ -#define SCSMR_0 0xE8007000 -#define SCIF0_BASE SCSMR_0 -#define SCSMR_1 0xE8007800 -#define SCIF1_BASE SCSMR_1 -#define SCSMR_2 0xE8008000 -#define SCIF2_BASE SCSMR_2 -#define SCSMR_3 0xE8008800 -#define SCIF3_BASE SCSMR_3 -#define SCSMR_7 0xE800A800 -#define SCIF7_BASE SCSMR_7 - -/* Timer(CMT) */ -#define CMSTR 0xFFFEC000 -#define CMCSR_0 0xFFFEC002 -#define CMCNT_0 0xFFFEC004 -#define CMCOR_0 0xFFFEC006 - -#endif /* _ASM_CPU_SH7269_H_ */ diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index b07fe542e3..bdc1da6295 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -1,8 +1,6 @@ #ifndef _ASM_SH_PROCESSOR_H_ #define _ASM_SH_PROCESSOR_H_ -#if defined(CONFIG_CPU_SH2) -# include <asm/cpu_sh2.h> -#elif defined(CONFIG_CPU_SH3) +#if defined(CONFIG_CPU_SH3) # include <asm/cpu_sh3.h> #elif defined(CONFIG_CPU_SH4) # include <asm/cpu_sh4.h> |