Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86

- Move P2SB from Apollo Lake to a more generic location
- Add a function to find a device by drvdata in DM core
- Enhancement of DM IRQ uclass driver
- Add a clock driver for Intel devices
- Add support for ACPI general-purpose events
- Add a TPM driver for H1/Cr50
- Enable TPM on Google Chromebook Coral

4 files changed, 7 insertions, 231 deletions

diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index a760e0ac68..942f11f566 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -40,6 +40,11 @@ config INTEL_APOLLOLAKE
 	imply INTEL_GPIO
 	imply SMP
 	imply HAVE_ITSS
+	imply HAVE_P2SB
+	imply CLK
+	imply CMD_CLK
+	imply CLK_INTEL
+	imply ACPI_GPE
 
 if INTEL_APOLLOLAKE
 
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index f99f2c6473..578e15c4bf 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -20,7 +20,6 @@ endif
 
 obj-y += hostbridge.o
 obj-y += lpc.o
-obj-y += p2sb.o
 obj-y += pch.o
 obj-y += pmc.o
 obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 9804227f80..b2d9130841 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -24,7 +24,6 @@
 #define HIDE_BIT		BIT(0)
 
 #define INTEL_GSPI_MAX		3
-#define INTEL_I2C_DEV_MAX	8
 #define MAX_USB2_PORTS		8
 
 enum {
@@ -32,36 +31,6 @@ enum {
 	CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
 };
 
-enum i2c_speed {
-	I2C_SPEED_STANDARD	= 100000,
-	I2C_SPEED_FAST		= 400000,
-	I2C_SPEED_FAST_PLUS	= 1000000,
-	I2C_SPEED_HIGH		= 3400000,
-	I2C_SPEED_FAST_ULTRA	= 5000000,
-};
-
-/*
- * Timing values are in units of clock period, with the clock speed
- * provided by the SOC
- *
- * TODO(sjg@chromium.org): Connect this up to the I2C driver
- */
-struct dw_i2c_speed_config {
-	enum i2c_speed speed;
-	/* SCL high and low period count */
-	u16 scl_lcnt;
-	u16 scl_hcnt;
-	/*
-	 * SDA hold time should be 300ns in standard and fast modes
-	 * and long enough for deterministic logic level change in
-	 * fast-plus and high speed modes.
-	 *
-	 *  [15:0] SDA TX Hold Time
-	 * [23:16] SDA RX Hold Time
-	 */
-	u32 sda_hold;
-};
-
 /* Serial IRQ control. SERIRQ_QUIET is the default (0) */
 enum serirq_mode {
 	SERIRQ_QUIET,
@@ -69,32 +38,6 @@ enum serirq_mode {
 	SERIRQ_OFF,
 };
 
-/*
- * This I2C controller has support for 3 independent speed configs but can
- * support both FAST_PLUS and HIGH speeds through the same set of speed
- * config registers.  These are treated separately so the speed config values
- * can be provided via ACPI to the OS.
- */
-#define DW_I2C_SPEED_CONFIG_COUNT	4
-
-struct dw_i2c_bus_config {
-	/* Bus should be enabled in TPL with temporary base */
-	int early_init;
-	/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
-	enum i2c_speed speed;
-	/*
-	 * If rise_time_ns is non-zero the calculations for lcnt and hcnt
-	 * registers take into account the times of the bus. However, if
-	 * there is a match in speed_config those register values take
-	 * precedence
-	 */
-	int rise_time_ns;
-	int fall_time_ns;
-	int data_hold_time_ns;
-	/* Specific bus speed configuration */
-	struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT];
-};
-
 struct gspi_cfg {
 	/* Bus speed in MHz */
 	u32 speed_mhz;
@@ -110,7 +53,6 @@ struct gspi_cfg {
 struct soc_intel_common_config {
 	int chipset_lockdown;
 	struct gspi_cfg gspi[INTEL_GSPI_MAX];
-	struct dw_i2c_bus_config i2c[INTEL_I2C_DEV_MAX];
 };
 
 enum pnp_settings {
@@ -593,7 +535,7 @@ int arch_fsps_preinit(void)
 	struct udevice *itss;
 	int ret;
 
-	ret = uclass_first_device_err(UCLASS_IRQ, &itss);
+	ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
 	if (ret)
 		return log_msg_ret("no itss", ret);
 	/*
@@ -634,7 +576,7 @@ int arch_fsp_init_r(void)
 	if (ret)
 		return ret;
 
-	ret = uclass_first_device_err(UCLASS_IRQ, &itss);
+	ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
 	if (ret)
 		return log_msg_ret("no itss", ret);
 	/* Restore GPIO IRQ polarities back to previous settings */
diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c
deleted file mode 100644
index b72f50a627..0000000000
--- a/arch/x86/cpu/apollolake/p2sb.c
+++ /dev/null
@@ -1,170 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Primary-to-Sideband Bridge
- *
- * Copyright 2019 Google LLC
- */
-
-#define LOG_CATEGORY UCLASS_P2SB
-
-#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-#include <p2sb.h>
-#include <spl.h>
-#include <asm/pci.h>
-
-struct p2sb_platdata {
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-	struct dtd_intel_apl_p2sb dtplat;
-#endif
-	ulong mmio_base;
-	pci_dev_t bdf;
-};
-
-/* PCI config space registers */
-#define HPTC_OFFSET		0x60
-#define HPTC_ADDR_ENABLE_BIT	BIT(7)
-
-/* High Performance Event Timer Configuration */
-#define P2SB_HPTC				0x60
-#define P2SB_HPTC_ADDRESS_ENABLE		BIT(7)
-
-/*
- * ADDRESS_SELECT            ENCODING_RANGE
- *      0                 0xfed0 0000 - 0xfed0 03ff
- *      1                 0xfed0 1000 - 0xfed0 13ff
- *      2                 0xfed0 2000 - 0xfed0 23ff
- *      3                 0xfed0 3000 - 0xfed0 33ff
- */
-#define P2SB_HPTC_ADDRESS_SELECT_0		(0 << 0)
-#define P2SB_HPTC_ADDRESS_SELECT_1		(1 << 0)
-#define P2SB_HPTC_ADDRESS_SELECT_2		(2 << 0)
-#define P2SB_HPTC_ADDRESS_SELECT_3		(3 << 0)
-
-/*
- * apl_p2sb_early_init() - Enable decoding for HPET range
- *
- * This is needed by FSP-M which uses the High Precision Event Timer.
- *
- * @dev: P2SB device
- * @return 0 if OK, -ve on error
- */
-static int apl_p2sb_early_init(struct udevice *dev)
-{
-	struct p2sb_platdata *plat = dev_get_platdata(dev);
-	pci_dev_t pdev = plat->bdf;
-
-	/*
-	 * Enable decoding for HPET memory address range.
-	 * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
-	 * the High Performance Timer memory address range
-	 * selected by bits 1:0
-	 */
-	pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
-			     PCI_SIZE_8);
-
-	/* Enable PCR Base address in PCH */
-	pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
-			     PCI_SIZE_32);
-	pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
-
-	/* Enable P2SB MSE */
-	pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
-			     PCI_COMMAND_MEMORY, PCI_SIZE_8);
-
-	return 0;
-}
-
-static int apl_p2sb_spl_init(struct udevice *dev)
-{
-	/* Enable decoding for HPET. Needed for FSP global pointer storage */
-	dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
-			    P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
-
-	return 0;
-}
-
-int apl_p2sb_ofdata_to_platdata(struct udevice *dev)
-{
-	struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
-	struct p2sb_platdata *plat = dev_get_platdata(dev);
-
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-	int ret;
-
-	if (spl_phase() == PHASE_TPL) {
-		u32 base[2];
-
-		/* TPL sets up the initial BAR */
-		ret = dev_read_u32_array(dev, "early-regs", base,
-					 ARRAY_SIZE(base));
-		if (ret)
-			return log_msg_ret("Missing/short early-regs", ret);
-		plat->mmio_base = base[0];
-		plat->bdf = pci_get_devfn(dev);
-		if (plat->bdf < 0)
-			return log_msg_ret("Cannot get p2sb PCI address",
-					   plat->bdf);
-	}
-#else
-	plat->mmio_base = plat->dtplat.early_regs[0];
-	plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
-#endif
-	upriv->mmio_base = plat->mmio_base;
-	debug("p2sb: mmio_base=%x\n", (uint)plat->mmio_base);
-
-	return 0;
-}
-
-static int apl_p2sb_probe(struct udevice *dev)
-{
-	if (spl_phase() == PHASE_TPL) {
-		return apl_p2sb_early_init(dev);
-	} else {
-		struct p2sb_platdata *plat = dev_get_platdata(dev);
-
-		plat->mmio_base = dev_read_addr_pci(dev);
-		/* Don't set BDF since it should not be used */
-		if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE)
-			return -EINVAL;
-
-		if (spl_phase() == PHASE_SPL)
-			return apl_p2sb_spl_init(dev);
-	}
-
-	return 0;
-}
-
-static int p2sb_child_post_bind(struct udevice *dev)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-	struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
-	int ret;
-	u32 pid;
-
-	ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
-	if (ret)
-		return ret;
-	pplat->pid = pid;
-#endif
-
-	return 0;
-}
-
-static const struct udevice_id apl_p2sb_ids[] = {
-	{ .compatible = "intel,apl-p2sb" },
-	{ }
-};
-
-U_BOOT_DRIVER(apl_p2sb_drv) = {
-	.name		= "intel_apl_p2sb",
-	.id		= UCLASS_P2SB,
-	.of_match	= apl_p2sb_ids,
-	.probe		= apl_p2sb_probe,
-	.ofdata_to_platdata = apl_p2sb_ofdata_to_platdata,
-	.platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
-	.per_child_platdata_auto_alloc_size =
-		sizeof(struct p2sb_child_platdata),
-	.child_post_bind = p2sb_child_post_bind,
-};