diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2017-08-15 22:41:58 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2017-09-16 14:57:44 +0800 |
| commit | de9ac9a1b9c0899d05d582917330092d577d5ebe (patch) | |
| tree | b290700167bcb6395540951993d8f08e3dce64c9 /arch/x86/cpu/braswell/Kconfig | |
| parent | b3fd2126dc8114d648b1e769b9fa621e3537bf48 (diff) | |
x86: Add Intel Braswell SoC support
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.
Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/braswell/Kconfig')
| -rw-r--r-- | arch/x86/cpu/braswell/Kconfig | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig new file mode 100644 index 0000000000..0e214a7432 --- /dev/null +++ b/arch/x86/cpu/braswell/Kconfig @@ -0,0 +1,39 @@ +# +# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_BRASWELL + bool + select HAVE_FSP + select ARCH_MISC_INIT + select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED + imply HAVE_INTEL_ME + imply HAVE_VBT + imply ENABLE_MRC_CACHE + imply ENV_IS_IN_SPI_FLASH + imply AHCI_PCI + imply ICH_SPI + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply SCSI + imply SPI_FLASH + imply SYS_NS16550 + imply USB + imply USB_XHCI_HCD + imply VIDEO_FSP + +if INTEL_BRASWELL + +config FSP_ADDR + hex + default 0xfff20000 + +config FSP_LOCKDOWN_SPI + bool + default y + +endif |