diff options
| author | Simon Glass <sjg@chromium.org> | 2019-12-06 21:42:25 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 11:44:18 +0800 |
| commit | f45e747d6d0b107992e8aed74c001034c8a6f1a1 (patch) | |
| tree | 8f39a274ed8a75083893cf1899d64f242ab11059 /arch/x86/cpu/intel_common/Makefile | |
| parent | 2e2a0035d4ab520615fd13dc7c89a60a44eb6bc0 (diff) | |
x86: Add support for newer CAR schemes
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.
To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/intel_common/Makefile')
| -rw-r--r-- | arch/x86/cpu/intel_common/Makefile | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index dfbc29f047..09212cee04 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -8,6 +8,14 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o endif + +ifdef CONFIG_INTEL_CAR_CQOS +obj-$(CONFIG_TPL_BUILD) += car2.o +ifndef CONFIG_SPL_BUILD +obj-y += car2_uninit.o +endif +endif + obj-y += cpu.o obj-y += fast_spi.o obj-y += lpc.o |