diff options
| author | Simon Glass <sjg@chromium.org> | 2016-03-11 22:07:09 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 10:27:25 +0800 |
| commit | 6bcb675b2f6a3251d0107673949988c619ec18ec (patch) | |
| tree | bb3ecbbc6c754ed19c78f12c5afc721de7a3eb97 /arch/x86/cpu/intel_common/microcode.c | |
| parent | f7d35bc148de7ebca7f51a07fc9a45715f8e6d29 (diff) | |
x86: Record the CPU details when starting each core
As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/intel_common/microcode.c')
| -rw-r--r-- | arch/x86/cpu/intel_common/microcode.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/x86/cpu/intel_common/microcode.c b/arch/x86/cpu/intel_common/microcode.c index 3054fabfde..daf0d69494 100644 --- a/arch/x86/cpu/intel_common/microcode.c +++ b/arch/x86/cpu/intel_common/microcode.c @@ -64,8 +64,12 @@ static int microcode_decode_node(const void *blob, int node, return 0; } -static inline uint32_t microcode_read_rev(void) +int microcode_read_rev(void) { + /* Quark does not have microcode MSRs */ +#ifdef CONFIG_INTEL_QUARK + return 0; +#else /* * Some Intel CPUs can be very finicky about the CPUID sequence used. * So this is implemented in assembly so that it works reliably. @@ -90,6 +94,7 @@ static inline uint32_t microcode_read_rev(void) ); return high; +#endif } static void microcode_read_cpu(struct microcode_update *cpu) |