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authorTom Rini <trini@konsulko.com>2019-10-08 18:45:26 -0400
committerTom Rini <trini@konsulko.com>2019-10-08 18:45:26 -0400
commitefea5a34bb5be542630ce7161bd3b9cc26a0bcf3 (patch)
treefb747d83d81f9c3400a561782114e4c6ecd61a07 /arch/x86/cpu/ivybridge/cpu.c
parent9d536fe8ae7672bdee091f9100389b6f3e53cfc6 (diff)
parentcc2d27dcdc3e1c76d09d54015e3992380bd7e0fa (diff)
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Rename existing FSP code to fsp1 - Add fsp2 directory in preparation to support FSP 2.0 - Various x86 platform codes update - Various bug fixes and updates in dm core, sandbox and spl
Diffstat (limited to 'arch/x86/cpu/ivybridge/cpu.c')
-rw-r--r--arch/x86/cpu/ivybridge/cpu.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index c8b16e32c0..6db9da81b7 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -199,6 +199,5 @@ int print_cpuinfo(void)
void board_debug_uart_init(void)
{
/* This enables the debug UART */
- pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN,
- PCI_SIZE_16);
+ pci_x86_write_config(PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, PCI_SIZE_16);
}