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authorSimon Glass <sjg@chromium.org>2015-03-05 12:25:15 -0700
committerSimon Glass <sjg@chromium.org>2015-04-16 19:27:41 -0600
commit31f57c28736d9a070fe56c55d57e9da406ee86ba (patch)
tree9d3d2bacb65e48e1ac21ec1c08f852f9f04936c2 /arch/x86/cpu/ivybridge/northbridge.c
parent5f7bfdd63094689af501fdef77423e0029c06622 (diff)
x86: Add a x86_ prefix to the x86-specific PCI functions
These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/ivybridge/northbridge.c')
-rw-r--r--arch/x86/cpu/ivybridge/northbridge.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index c50b5ded83..e95e60e519 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -30,7 +30,7 @@ int bridge_silicon_revision(void)
result = cpuid(1);
stepping = result.eax & 0xf;
dev = PCI_BDF(0, 0, 0);
- bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
+ bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
bridge_revision_id = bridge_id | stepping;
}
@@ -55,7 +55,7 @@ static int get_pcie_bar(u32 *base, u32 *len)
*base = 0;
*len = 0;
- pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+ pciexbar_reg = x86_pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0)))
return 0;
@@ -170,7 +170,7 @@ void northbridge_init(pci_dev_t dev)
void northbridge_enable(pci_dev_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME
- switch (pci_read_config32(dev, SKPAD)) {
+ switch (x86_pci_read_config32(dev, SKPAD)) {
case 0xcafebabe:
debug("Normal boot.\n");
apci_set_slp_type(0);