diff options
| author | Simon Glass <sjg@chromium.org> | 2014-11-14 18:18:42 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-11-25 06:34:02 -0700 |
| commit | a6d4c453069303c3d1a499d2282f423b35c8f3b0 (patch) | |
| tree | 23daeaee24c32957e42d9bb9ba90c76c2f92a7b4 /arch/x86/cpu/ivybridge/usb_xhci.c | |
| parent | 79b303467a2aede83dd355b46e4dadbd5b40f0ac (diff) | |
x86: ivybridge: Set up XHCI USB
Add init for XHCI so that high-speed USB can be used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/ivybridge/usb_xhci.c')
| -rw-r--r-- | arch/x86/cpu/ivybridge/usb_xhci.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c new file mode 100644 index 0000000000..4a32a7eb31 --- /dev/null +++ b/arch/x86/cpu/ivybridge/usb_xhci.c @@ -0,0 +1,32 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/pci.h> +#include <asm/arch/pch.h> + +void bd82x6x_usb_xhci_init(pci_dev_t dev) +{ + u32 reg32; + + debug("XHCI: Setting up controller.. "); + + /* lock overcurrent map */ + reg32 = pci_read_config32(dev, 0x44); + reg32 |= 1; + pci_write_config32(dev, 0x44, reg32); + + /* Enable clock gating */ + reg32 = pci_read_config32(dev, 0x40); + reg32 &= ~((1 << 20) | (1 << 21)); + reg32 |= (1 << 19) | (1 << 18) | (1 << 17); + reg32 |= (1 << 10) | (1 << 9) | (1 << 8); + reg32 |= (1 << 31); /* lock */ + pci_write_config32(dev, 0x40, reg32); + + debug("done.\n"); +} |