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authorBin Meng <bmeng.cn@gmail.com>2015-10-11 21:37:36 -0700
committerSimon Glass <sjg@chromium.org>2015-10-21 07:46:26 -0600
commitf6220f1a86109f88950fd42e3af54314de24365a (patch)
tree4749256576c9bb19a1f71ecc0ca1b09bbe07a854 /arch/x86/cpu/ivybridge
parente2d76e95d3f048a171ccd65ea0bd954ccc2b15e0 (diff)
x86: Move mrccache.[c|h] to a common place
mrccache implementation can be common for all boards. Move it from ivybridge cpu directory to the common lib directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/ivybridge')
-rw-r--r--arch/x86/cpu/ivybridge/Makefile1
-rw-r--r--arch/x86/cpu/ivybridge/mrccache.c157
-rw-r--r--arch/x86/cpu/ivybridge/sdram.c2
3 files changed, 1 insertions, 159 deletions
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 3576b83266..0c7efaec7c 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -14,7 +14,6 @@ obj-y += lpc.o
obj-y += me_status.o
obj-y += model_206ax.o
obj-y += microcode_intel.o
-obj-y += mrccache.o
obj-y += northbridge.o
obj-y += pch.o
obj-y += pci.o
diff --git a/arch/x86/cpu/ivybridge/mrccache.c b/arch/x86/cpu/ivybridge/mrccache.c
deleted file mode 100644
index 92054948eb..0000000000
--- a/arch/x86/cpu/ivybridge/mrccache.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * From Coreboot src/southbridge/intel/bd82x6x/mrccache.c
- *
- * Copyright (C) 2014 Google Inc.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <errno.h>
-#include <fdtdec.h>
-#include <net.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <asm/arch/mrccache.h>
-#include <asm/arch/sandybridge.h>
-
-static struct mrc_data_container *next_mrc_block(
- struct mrc_data_container *mrc_cache)
-{
- /* MRC data blocks are aligned within the region */
- u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->data_size;
- if (mrc_size & (MRC_DATA_ALIGN - 1UL)) {
- mrc_size &= ~(MRC_DATA_ALIGN - 1UL);
- mrc_size += MRC_DATA_ALIGN;
- }
-
- u8 *region_ptr = (u8 *)mrc_cache;
- region_ptr += mrc_size;
- return (struct mrc_data_container *)region_ptr;
-}
-
-static int is_mrc_cache(struct mrc_data_container *cache)
-{
- return cache && (cache->signature == MRC_DATA_SIGNATURE);
-}
-
-/*
- * Find the largest index block in the MRC cache. Return NULL if none is
- * found.
- */
-struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry)
-{
- struct mrc_data_container *cache, *next;
- ulong base_addr, end_addr;
- uint id;
-
- base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset;
- end_addr = base_addr + entry->length;
- cache = NULL;
-
- /* Search for the last filled entry in the region */
- for (id = 0, next = (struct mrc_data_container *)base_addr;
- is_mrc_cache(next);
- id++) {
- cache = next;
- next = next_mrc_block(next);
- if ((ulong)next >= end_addr)
- break;
- }
-
- if (id-- == 0) {
- debug("%s: No valid MRC cache found.\n", __func__);
- return NULL;
- }
-
- /* Verify checksum */
- if (cache->checksum != compute_ip_checksum(cache->data,
- cache->data_size)) {
- printf("%s: MRC cache checksum mismatch\n", __func__);
- return NULL;
- }
-
- debug("%s: picked entry %u from cache block\n", __func__, id);
-
- return cache;
-}
-
-/**
- * find_next_mrc_cache() - get next cache entry
- *
- * @entry: MRC cache flash area
- * @cache: Entry to start from
- *
- * @return next cache entry if found, NULL if we got to the end
- */
-static struct mrc_data_container *find_next_mrc_cache(struct fmap_entry *entry,
- struct mrc_data_container *cache)
-{
- ulong base_addr, end_addr;
-
- base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset;
- end_addr = base_addr + entry->length;
-
- cache = next_mrc_block(cache);
- if ((ulong)cache >= end_addr) {
- /* Crossed the boundary */
- cache = NULL;
- debug("%s: no available entries found\n", __func__);
- } else {
- debug("%s: picked next entry from cache block at %p\n",
- __func__, cache);
- }
-
- return cache;
-}
-
-int mrccache_update(struct udevice *sf, struct fmap_entry *entry,
- struct mrc_data_container *cur)
-{
- struct mrc_data_container *cache;
- ulong offset;
- ulong base_addr;
- int ret;
-
- /* Find the last used block */
- base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset;
- debug("Updating MRC cache data\n");
- cache = mrccache_find_current(entry);
- if (cache && (cache->data_size == cur->data_size) &&
- (!memcmp(cache, cur, cache->data_size + sizeof(*cur)))) {
- debug("MRC data in flash is up to date. No update\n");
- return -EEXIST;
- }
-
- /* Move to the next block, which will be the first unused block */
- if (cache)
- cache = find_next_mrc_cache(entry, cache);
-
- /*
- * If we have got to the end, erase the entire mrc-cache area and start
- * again at block 0.
- */
- if (!cache) {
- debug("Erasing the MRC cache region of %x bytes at %x\n",
- entry->length, entry->offset);
-
- ret = spi_flash_erase_dm(sf, entry->offset, entry->length);
- if (ret) {
- debug("Failed to erase flash region\n");
- return ret;
- }
- cache = (struct mrc_data_container *)base_addr;
- }
-
- /* Write the data out */
- offset = (ulong)cache - base_addr + entry->offset;
- debug("Write MRC cache update to flash at %lx\n", offset);
- ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur),
- cur);
- if (ret) {
- debug("Failed to write to SPI flash\n");
- return ret;
- }
-
- return 0;
-}
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 7f3b13d357..10fbe5fb36 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -21,10 +21,10 @@
#include <asm/processor.h>
#include <asm/gpio.h>
#include <asm/global_data.h>
+#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/pci.h>
#include <asm/arch/me.h>
-#include <asm/arch/mrccache.h>
#include <asm/arch/pei_data.h>
#include <asm/arch/pch.h>
#include <asm/post.h>