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authorBin Meng <bmeng.cn@gmail.com>2015-09-11 03:24:36 -0700
committerSimon Glass <sjg@chromium.org>2015-09-16 19:53:52 -0600
commit5841c5b0a7967364a8ec10d54ab77ad62f3ab164 (patch)
tree9de121ce2f2daf10b6fcb20e83703938c5f920c2 /arch/x86/cpu/quark
parent8b7ee66cec950899eace0caf729cf2100155020a (diff)
x86: Convert to use driver model eth on quark/galileo
Convert to use DM version of Designware ethernet driver on Intel quark/galileo. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/quark')
-rw-r--r--arch/x86/cpu/quark/quark.c19
1 files changed, 0 insertions, 19 deletions
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 637c370e81..caa3875cc4 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -6,8 +6,6 @@
#include <common.h>
#include <mmc.h>
-#include <netdev.h>
-#include <phy.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
@@ -231,23 +229,6 @@ int cpu_mmc_init(bd_t *bis)
ARRAY_SIZE(mmc_supported));
}
-int cpu_eth_init(bd_t *bis)
-{
- u32 base;
- int ret0, ret1;
-
- qrk_pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base);
- ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
-
- qrk_pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base);
- ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
-
- if (ret0 < 0 && ret1 < 0)
- return -1;
- else
- return 0;
-}
-
void cpu_irq_init(void)
{
struct quark_rcba *rcba;