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authorBin Meng <bmeng.cn@gmail.com>2015-03-11 11:25:56 +0800
committerSimon Glass <sjg@chromium.org>2015-03-24 21:22:37 -0600
commite4ad6031a79fb3182613f95423ebcd771309679d (patch)
tree6697cac639d4ed5776754642ef932c63d5b31398 /arch/x86/cpu/quark
parent83d9712e70dcd704462a3dc53254a05087c231f0 (diff)
x86: quark: Enable on-chip ethernet controllers
Intel Quark SoC integrates two 10/100 ethernet controllers which can be connected to an external RMII PHY. The MAC IP is from Designware. Enable this support with the existing U-Boot Designware MAC driver so that the ethernet port on Intel Galileo board can be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/quark')
-rw-r--r--arch/x86/cpu/quark/quark.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index dccf7ac5f5..25edcf71cb 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -6,6 +6,8 @@
#include <common.h>
#include <mmc.h>
+#include <netdev.h>
+#include <phy.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/post.h>
@@ -116,3 +118,20 @@ int cpu_mmc_init(bd_t *bis)
return pci_mmc_init("Quark SDHCI", mmc_supported,
ARRAY_SIZE(mmc_supported));
}
+
+int cpu_eth_init(bd_t *bis)
+{
+ u32 base;
+ int ret0, ret1;
+
+ pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base);
+ ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
+
+ pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base);
+ ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
+
+ if (ret0 < 0 && ret1 < 0)
+ return -1;
+ else
+ return 0;
+}