x86: irq: Remove chipset specific irq router drivers

At present there are 3 irq router drivers. One is the common one
and the other two are chipset specific for queensbay and quark.
However these are really the same drivers as the core logic is
the same. The two chipset specific drivers configure some registers
that are outside the irq router block which should really be part
of the chipset initialization.

Now we remove these specific drivers and make all x86 boards use
the common one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

3 files changed, 40 insertions, 65 deletions

diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index b535b2a406..ac2961356b 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -2,5 +2,5 @@
 #
 # Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
 
-obj-y += fsp_configs.o irq.o
+obj-y += fsp_configs.o
 obj-y += tnc.o
diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c
deleted file mode 100644
index 208cd61b55..0000000000
--- a/arch/x86/cpu/queensbay/irq.c
+++ /dev/null
@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- * Copyright (C) 2015 Google, Inc
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/pci.h>
-#include <asm/arch/device.h>
-#include <asm/arch/tnc.h>
-
-int queensbay_irq_router_probe(struct udevice *dev)
-{
-	struct tnc_rcba *rcba;
-	u32 base;
-
-	dm_pci_read_config32(dev->parent, LPC_RCBA, &base);
-	base &= ~MEM_BAR_EN;
-	rcba = (struct tnc_rcba *)base;
-
-	/* Make sure all internal PCI devices are using INTA */
-	writel(INTA, &rcba->d02ip);
-	writel(INTA, &rcba->d03ip);
-	writel(INTA, &rcba->d27ip);
-	writel(INTA, &rcba->d31ip);
-	writel(INTA, &rcba->d23ip);
-	writel(INTA, &rcba->d24ip);
-	writel(INTA, &rcba->d25ip);
-	writel(INTA, &rcba->d26ip);
-
-	/*
-	 * Route TunnelCreek PCI device interrupt pin to PIRQ
-	 *
-	 * Since PCIe downstream ports received INTx are routed to PIRQ
-	 * A/B/C/D directly and not configurable, we have to route PCIe
-	 * root ports' INTx to PIRQ A/B/C/D as well. For other devices
-	 * on TunneCreek, route them to PIRQ E/F/G/H.
-	 */
-	writew(PIRQE, &rcba->d02ir);
-	writew(PIRQF, &rcba->d03ir);
-	writew(PIRQG, &rcba->d27ir);
-	writew(PIRQH, &rcba->d31ir);
-	writew(PIRQA, &rcba->d23ir);
-	writew(PIRQB, &rcba->d24ir);
-	writew(PIRQC, &rcba->d25ir);
-	writew(PIRQD, &rcba->d26ir);
-
-	return irq_router_common_init(dev);
-}
-
-static const struct udevice_id queensbay_irq_router_ids[] = {
-	{ .compatible = "intel,queensbay-irq-router" },
-	{ }
-};
-
-U_BOOT_DRIVER(queensbay_irq_router_drv) = {
-	.name		= "queensbay_intel_irq",
-	.id		= UCLASS_IRQ,
-	.of_match	= queensbay_irq_router_ids,
-	.probe		= queensbay_irq_router_probe,
-};
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 439c14d8bc..76556fc7f7 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -98,6 +98,43 @@ int arch_cpu_init(void)
 	return x86_cpu_init_f();
 }
 
+static void tnc_irq_init(void)
+{
+	struct tnc_rcba *rcba;
+	u32 base;
+
+	pci_read_config32(TNC_LPC, LPC_RCBA, &base);
+	base &= ~MEM_BAR_EN;
+	rcba = (struct tnc_rcba *)base;
+
+	/* Make sure all internal PCI devices are using INTA */
+	writel(INTA, &rcba->d02ip);
+	writel(INTA, &rcba->d03ip);
+	writel(INTA, &rcba->d27ip);
+	writel(INTA, &rcba->d31ip);
+	writel(INTA, &rcba->d23ip);
+	writel(INTA, &rcba->d24ip);
+	writel(INTA, &rcba->d25ip);
+	writel(INTA, &rcba->d26ip);
+
+	/*
+	 * Route TunnelCreek PCI device interrupt pin to PIRQ
+	 *
+	 * Since PCIe downstream ports received INTx are routed to PIRQ
+	 * A/B/C/D directly and not configurable, we have to route PCIe
+	 * root ports' INTx to PIRQ A/B/C/D as well. For other devices
+	 * on TunneCreek, route them to PIRQ E/F/G/H.
+	 */
+	writew(PIRQE, &rcba->d02ir);
+	writew(PIRQF, &rcba->d03ir);
+	writew(PIRQG, &rcba->d27ir);
+	writew(PIRQH, &rcba->d31ir);
+	writew(PIRQA, &rcba->d23ir);
+	writew(PIRQB, &rcba->d24ir);
+	writew(PIRQC, &rcba->d25ir);
+	writew(PIRQD, &rcba->d26ir);
+}
+
 int arch_early_init_r(void)
 {
 	int ret = 0;
@@ -106,5 +143,7 @@ int arch_early_init_r(void)
 	ret = disable_igd();
 #endif
 
+	tnc_irq_init();
+
 	return ret;
 }