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authorSimon Glass <sjg@chromium.org>2019-12-06 21:42:01 -0700
committerBin Meng <bmeng.cn@gmail.com>2019-12-15 11:44:12 +0800
commit112629c53a488fd87e3b6116f16ce768e8930f94 (patch)
treeaad889f23a3c1c6937d43050c99847e7783c9163 /arch/x86/cpu/tangier
parentb93757caa122fc52bccb573df1c16c478eef6b2f (diff)
x86: Reduce mrccache record alignment size
At present the records are 4KB in size. This is unnecessarily large when the SPI-flash erase size is 256 bytes. Reduce it so it will be more efficient with Apollo Lake's 24-byte variable-data record. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/tangier')
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