diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2015-02-04 16:26:12 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-02-06 12:07:45 -0700 |
| commit | 728b393f3b012ac46505151b80af1d4334786845 (patch) | |
| tree | f7a9eaa7476cad5432886ee7d121044d7adc035a /arch/x86/cpu | |
| parent | 38fc1cdae0fb7a429222b7b85f8cdaefbd078e21 (diff) | |
x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/quark/quark.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index cf596e45e1..0d593d9a86 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -13,6 +13,21 @@ #include <asm/arch/msg_port.h> #include <asm/arch/quark.h> +/* + * TODO: + * + * This whole routine should be removed until we fully convert the ICH SPI + * driver to DM and make use of DT to pass the bios control register offset + */ +static void unprotect_spi_flash(void) +{ + u32 bc; + + bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8); + bc |= 0x1; /* unprotect the flash */ + pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc); +} + static void quark_setup_bars(void) { /* GPIO - D31:F0:R44h */ @@ -74,6 +89,8 @@ int arch_cpu_init(void) */ quark_setup_bars(); + unprotect_spi_flash(); + return 0; } |