Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86

- Enable SD slot on Intel Edison
- Populate CSRT ACPI table for shared DMA controller on Intel Tangier
- Convert Intel ICH-SPI driver to use new spi-mem ops
- Enable config_distro_bootcmd for QEMU x86
- Support U-Boot as a payload for Intel Slim Bootloader
- Avoid writing temporary asl files into the source tree which fixes the
  parallel build issue occasionally seen

9 files changed, 357 insertions, 2 deletions

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 85fd5e616e..3f1f62da2b 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
 obj-$(CONFIG_INTEL_BRASWELL) += braswell/
 obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
+obj-$(CONFIG_SYS_SLIMBOOTLOADER) += slimbootloader/
 obj-$(CONFIG_EFI) += efi/
 obj-$(CONFIG_QEMU) += qemu/
 obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
diff --git a/arch/x86/cpu/slimbootloader/Kconfig b/arch/x86/cpu/slimbootloader/Kconfig
new file mode 100644
index 0000000000..3ea4c9958c
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Intel Corporation <www.intel.com>
+
+config SYS_SLIMBOOTLOADER
+	bool
+	select USE_HOB
+	imply SYS_NS16550
+	imply AHCI_PCI
+	imply SCSI
+	imply SCSI_AHCI
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply USB
+	imply USB_EHCI_HCD
+	imply USB_XHCI_HCD
+	imply E1000
diff --git a/arch/x86/cpu/slimbootloader/Makefile b/arch/x86/cpu/slimbootloader/Makefile
new file mode 100644
index 0000000000..aac9fa3db8
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Intel Corporation <www.intel.com>
+
+obj-y += car.o slimbootloader.o sdram.o serial.o
diff --git a/arch/x86/cpu/slimbootloader/car.S b/arch/x86/cpu/slimbootloader/car.S
new file mode 100644
index 0000000000..6e0304333c
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/car.S
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <generated/asm-offsets.h>
+
+.section .text
+
+.globl car_init
+car_init:
+	/* Get hob pointer parameter from previous stage's stack */
+	mov	0x4(%esp), %esi
+	jmp	car_init_ret
diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c
new file mode 100644
index 0000000000..05d40d196c
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/sdram.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/e820.h>
+#include <asm/arch/slimbootloader.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * This returns a data pointer of memory map info from the guid hob.
+ *
+ * @return: A data pointer of memory map info hob
+ */
+static struct sbl_memory_map_info *get_memory_map_info(void)
+{
+	struct sbl_memory_map_info *data;
+	const efi_guid_t guid = SBL_MEMORY_MAP_INFO_GUID;
+
+	if (!gd->arch.hob_list)
+		return NULL;
+
+	data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid);
+	if (!data)
+		panic("memory map info hob not found\n");
+	if (!data->count)
+		panic("invalid number of memory map entries\n");
+
+	return data;
+}
+
+#define for_each_if(condition) if (!(condition)) {} else
+
+#define for_each_memory_map_entry_reversed(iter, entries) \
+	for (iter = entries->count - 1; iter >= 0; iter--) \
+		for_each_if(entries->entry[iter].type == E820_RAM)
+
+/**
+ * This is to give usable memory region information for u-boot relocation.
+ * so search usable memory region lower than 4GB.
+ * The memory map entries from Slim Bootloader hob are already sorted.
+ *
+ * @total_size: The memory size that u-boot occupies
+ * @return    : The top available memory address lower than 4GB
+ */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	struct sbl_memory_map_info *data;
+	int i;
+	u64 addr_start;
+	u64 addr_end;
+	ulong ram_top;
+
+	data = get_memory_map_info();
+
+	/**
+	 * sorted memory map entries from Slim Bootloader based on physical
+	 * start memory address, from low to high. So do reversed search to
+	 * get highest usable, suitable size, 4KB aligned available memory
+	 * under 4GB.
+	 */
+	ram_top = 0;
+	for_each_memory_map_entry_reversed(i, data) {
+		addr_start = data->entry[i].addr;
+		addr_end = addr_start + data->entry[i].size;
+
+		if (addr_start > SZ_4G)
+			continue;
+
+		if (addr_end > SZ_4G)
+			addr_end = SZ_4G;
+
+		if (addr_end < total_size)
+			continue;
+
+		/* to relocate u-boot at 4K aligned memory */
+		addr_end = rounddown(addr_end - total_size, SZ_4K);
+		if (addr_end >= addr_start) {
+			ram_top = (ulong)addr_end + total_size;
+			break;
+		}
+	}
+
+	if (!ram_top)
+		panic("failed to find available memory for relocation!");
+
+	return ram_top;
+}
+
+/**
+ * The memory initialization has already been done in previous Slim Bootloader
+ * stage thru FSP-M. Instead, this sets the ram_size from the memory map info
+ * hob.
+ */
+int dram_init(void)
+{
+	struct sbl_memory_map_info *data;
+	int i;
+	u64 ram_size;
+
+	data = get_memory_map_info();
+
+	/**
+	 * sorted memory map entries from Slim Bootloader based on physical
+	 * start memory address, from low to high. So do reversed search to
+	 * simply get highest usable memory address as RAM size
+	 */
+	ram_size = 0;
+	for_each_memory_map_entry_reversed(i, data) {
+		/* simply use the highest usable memory address as RAM size */
+		ram_size = data->entry[i].addr + data->entry[i].size;
+		break;
+	}
+
+	if (!ram_size)
+		panic("failed to detect memory size");
+
+	gd->ram_size = ram_size;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	if (!CONFIG_NR_DRAM_BANKS)
+		return 0;
+
+	/* simply use a single bank to have whole size for now */
+	gd->bd->bi_dram[0].start = 0;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+	return 0;
+}
+
+unsigned int install_e820_map(unsigned int max_entries,
+			      struct e820_entry *entries)
+{
+	struct sbl_memory_map_info *data;
+	unsigned int i;
+
+	data = get_memory_map_info();
+
+	for (i = 0; i < data->count; i++) {
+		entries[i].addr = data->entry[i].addr;
+		entries[i].size = data->entry[i].size;
+		entries[i].type = data->entry[i].type;
+	}
+
+	return i;
+}
diff --git a/arch/x86/cpu/slimbootloader/serial.c b/arch/x86/cpu/slimbootloader/serial.c
new file mode 100644
index 0000000000..7b44a59bff
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/serial.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+#include <asm/arch/slimbootloader.h>
+
+/**
+ * The serial port info hob is generated by Slim Bootloader, so eligible for
+ * Slim Bootloader based boards only.
+ */
+static int slimbootloader_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	const efi_guid_t guid = SBL_SERIAL_PORT_INFO_GUID;
+	struct sbl_serial_port_info *data;
+	struct ns16550_platdata *plat = dev->platdata;
+
+	if (!gd->arch.hob_list)
+		panic("hob list not found!");
+
+	data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid);
+	if (!data) {
+		debug("failed to get serial port information\n");
+		return -ENOENT;
+	}
+	debug("type:%d base=0x%08x baudrate=%d stride=%d clk=%d\n",
+	      data->type,
+	      data->base,
+	      data->baud,
+	      data->stride,
+	      data->clk);
+
+	/*
+	 * The data->type provides port io or mmio access type info,
+	 * but the access type will be controlled by
+	 * CONFIG_SYS_NS16550_PORT_MAPPED or CONFIG_SYS_NS16550_MEM32.
+	 *
+	 * TBD: ns16550 access type configuration in runtime.
+	 *      ex) plat->access_type = data->type
+	 */
+	plat->base = data->base;
+	/* ns16550 uses reg_shift, then covert stride to shift */
+	plat->reg_shift = data->stride >> 1;
+	plat->clock = data->clk;
+
+	return 0;
+}
+
+static const struct udevice_id slimbootloader_serial_ids[] = {
+	{ .compatible = "intel,slimbootloader-uart" },
+	{}
+};
+
+U_BOOT_DRIVER(serial_slimbootloader) = {
+	.name	= "serial_slimbootloader",
+	.id	= UCLASS_SERIAL,
+	.of_match = slimbootloader_serial_ids,
+	.ofdata_to_platdata = slimbootloader_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+	.priv_auto_alloc_size = sizeof(struct NS16550),
+	.probe	= ns16550_serial_probe,
+	.ops	= &ns16550_serial_ops,
+};
diff --git a/arch/x86/cpu/slimbootloader/slimbootloader.c b/arch/x86/cpu/slimbootloader/slimbootloader.c
new file mode 100644
index 0000000000..e6b174ca88
--- /dev/null
+++ b/arch/x86/cpu/slimbootloader/slimbootloader.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <asm/arch/slimbootloader.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * This sets tsc_base and clock_rate for early_timer and tsc_timer.
+ * The performance info guid hob has all performance timestamp data, but
+ * the only tsc frequency info is used for the timer driver for now.
+ *
+ * Slim Bootloader already calibrated TSC and provides it to U-Boot.
+ * Therefore, U-Boot does not have to re-calibrate TSC.
+ * Configuring tsc_base and clock_rate here makes x86 tsc_timer driver
+ * bypass TSC calibration and use the provided TSC frequency.
+ */
+static void tsc_init(void)
+{
+	struct sbl_performance_info *data;
+	const efi_guid_t guid = SBL_PERFORMANCE_INFO_GUID;
+
+	if (!gd->arch.hob_list)
+		panic("hob list not found!");
+
+	gd->arch.tsc_base = rdtsc();
+	debug("tsc_base=0x%llx\n", gd->arch.tsc_base);
+
+	data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid);
+	if (!data) {
+		debug("performance info hob not found\n");
+		return;
+	}
+
+	/* frequency is in KHz, so to Hz */
+	gd->arch.clock_rate = data->frequency * 1000;
+	debug("freq=0x%lx\n", gd->arch.clock_rate);
+}
+
+int arch_cpu_init(void)
+{
+	tsc_init();
+
+	return x86_cpu_init_f();
+}
+
+int checkcpu(void)
+{
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	return default_print_cpuinfo();
+}
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 4a82add76b..71cd70f9cd 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -97,7 +97,7 @@ early_board_init_ret:
 	jmp	car_init
 .globl car_init_ret
 car_init_ret:
-#ifndef CONFIG_HAVE_FSP
+#ifndef CONFIG_USE_HOB
 	/*
 	 * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
 	 * or fully initialised SDRAM - we really don't care which)
@@ -137,12 +137,13 @@ car_init_ret:
 
 	/* Get address of global_data */
 	mov	%fs:0, %edx
-#ifdef CONFIG_HAVE_FSP
+#ifdef CONFIG_USE_HOB
 	/* Store the HOB list if we have one */
 	test	%esi, %esi
 	jz	skip_hob
 	movl	%esi, GD_HOB_LIST(%edx)
 
+#ifdef CONFIG_HAVE_FSP
 	/*
 	 * After fsp_init() returns, the stack has already been switched to a
 	 * place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
@@ -151,6 +152,7 @@ car_init_ret:
 	 */
 	subl	$CONFIG_FSP_SYS_MALLOC_F_LEN, %esp
 	movl	%esp, GD_MALLOC_BASE(%edx)
+#endif
 skip_hob:
 #else
 	/* Store table pointer */
diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c
index 0e4f961c53..61b2642aa9 100644
--- a/arch/x86/cpu/tangier/acpi.c
+++ b/arch/x86/cpu/tangier/acpi.c
@@ -68,6 +68,44 @@ u32 acpi_fill_mcfg(u32 current)
 	return current;
 }
 
+static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp)
+{
+	struct acpi_csrt_shared_info *si = (struct acpi_csrt_shared_info *)&grp[1];
+
+	/* Fill the Resource Group with Shared Information attached */
+	memset(grp, 0, sizeof(*grp));
+	grp->shared_info_length = sizeof(struct acpi_csrt_shared_info);
+	grp->length = sizeof(struct acpi_csrt_group) + grp->shared_info_length;
+	/* TODO: All values below should come from U-Boot DT somehow */
+	sprintf((char *)&grp->vendor_id, "%04X", 0x8086);
+	grp->device_id = 0x11a2;
+
+	/* Fill the Resource Group Shared Information */
+	memset(si, 0, sizeof(*si));
+	si->major_version = 1;
+	si->minor_version = 0;
+	/* TODO: All values below should come from U-Boot DT somehow */
+	si->mmio_base_low = 0xff192000;
+	si->mmio_base_high = 0;
+	si->gsi_interrupt = 32;
+	si->interrupt_polarity = 1;
+	si->interrupt_mode = 0;
+	si->num_channels = 8;
+	si->dma_address_width = 32;
+	si->base_request_line = 0;
+	si->num_handshake_signals = 16;
+	si->max_block_size = 0x20000;
+
+	return grp->length;
+}
+
+u32 acpi_fill_csrt(u32 current)
+{
+	current += acpi_fill_csrt_dma((struct acpi_csrt_group *)current);
+
+	return current;
+}
+
 void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
 {
 	struct udevice *dev;