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authorBin Meng <bmeng.cn@gmail.com>2017-05-31 01:04:15 -0700
committerBin Meng <bmeng.cn@gmail.com>2017-06-05 08:55:22 +0800
commitf8f291b0962c795fcb025338d5c2284e2357a669 (patch)
tree0cc3cea3163a8c0c35b0fecc67f99d2ea20e1007 /arch/x86/dts/bayleybay.dts
parent5e74e5a6826f8cf194ef5a569d6cafd2ed924f5c (diff)
x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer
At present lpe/lpss-sio/scc FSP properties are all boolean, but in fact for "enable-lpe" it has 3 possible options. This adds macros for these options and change the property from a boolean type to an integer type, and change their names to explicitly indicate what the property is really for. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts/bayleybay.dts')
-rw-r--r--arch/x86/dts/bayleybay.dts6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index a577b9371b..0c314e0688 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -248,8 +248,8 @@
fsp,enable-spi;
fsp,enable-sata;
fsp,sata-mode = <SATA_MODE_AHCI>;
- fsp,enable-lpe;
- fsp,lpss-sio-enable-pci-mode;
+ fsp,lpe-mode = <LPE_MODE_PCI>;
+ fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
fsp,enable-dma0;
fsp,enable-dma1;
fsp,enable-i2c0;
@@ -264,7 +264,7 @@
fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
fsp,aperture-size = <APERTURE_SIZE_256MB>;
fsp,gtt-size = <GTT_SIZE_2MB>;
- fsp,scc-enable-pci-mode;
+ fsp,scc-mode = <SCC_MODE_PCI>;
fsp,os-selection = <OS_SELECTION_LINUX>;
fsp,emmc45-ddr50-enabled;
fsp,emmc45-retune-timer-value = <8>;