summaryrefslogtreecommitdiff
path: root/arch/x86/dts/galileo.dts
diff options
context:
space:
mode:
authorBin Meng <bmeng.cn@gmail.com>2015-02-05 23:42:28 +0800
committerSimon Glass <sjg@chromium.org>2015-02-06 12:07:44 -0700
commit20c34115d603745cf276c683168292d02056791a (patch)
tree87362c3629bf18877689b87b3d58db2f6a55019c /arch/x86/dts/galileo.dts
parentb1420c813074d39cd2452d7bc45374561d1cf223 (diff)
x86: quark: Call MRC in dram_init()
Now that we have added Quark MRC codes, call MRC in dram_init() so that DRAM can be initialized on a Quark based board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts/galileo.dts')
-rw-r--r--arch/x86/dts/galileo.dts25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 14a19c3ec3..d462221a9d 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include <dt-bindings/mrc/quark.h>
+
/include/ "skeleton.dtsi"
/ {
@@ -20,6 +22,29 @@
stdout-path = &pciuart0;
};
+ mrc {
+ compatible = "intel,quark-mrc";
+ flags = <MRC_FLAG_SCRAMBLE_EN>;
+ dram-width = <DRAM_WIDTH_X8>;
+ dram-speed = <DRAM_FREQ_800>;
+ dram-type = <DRAM_TYPE_DDR3>;
+ rank-mask = <DRAM_RANK(0)>;
+ chan-mask = <DRAM_CHANNEL(0)>;
+ chan-width = <DRAM_CHANNEL_WIDTH_X16>;
+ addr-mode = <DRAM_ADDR_MODE0>;
+ refresh-rate = <DRAM_REFRESH_RATE_785US>;
+ sr-temp-range = <DRAM_SRT_RANGE_NORMAL>;
+ ron-value = <DRAM_RON_34OHM>;
+ rtt-nom-value = <DRAM_RTT_NOM_120OHM>;
+ rd-odt-value = <DRAM_RD_ODT_OFF>;
+ dram-density = <DRAM_DENSITY_1G>;
+ dram-cl = <6>;
+ dram-ras = <0x0000927c>;
+ dram-wtr = <0x00002710>;
+ dram-rrd = <0x00002710>;
+ dram-faw = <0x00009c40>;
+ };
+
pci {
#address-cells = <3>;
#size-cells = <2>;