diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2015-02-04 16:26:12 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-02-06 12:07:45 -0700 |
| commit | 728b393f3b012ac46505151b80af1d4334786845 (patch) | |
| tree | f7a9eaa7476cad5432886ee7d121044d7adc035a /arch/x86/dts/galileo.dts | |
| parent | 38fc1cdae0fb7a429222b7b85f8cdaefbd078e21 (diff) | |
x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts/galileo.dts')
| -rw-r--r-- | arch/x86/dts/galileo.dts | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 2f60aeb82d..66af64abda 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -79,4 +79,17 @@ bank-name = "B"; }; + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + }; + }; + }; |