diff options
| author | Tom Rini <trini@konsulko.com> | 2020-06-01 23:34:18 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-06-01 23:34:18 -0400 |
| commit | ecd4d99f654f3f7bfb96001891d69c3125e70b69 (patch) | |
| tree | 405530bb85d5fdc97aadd6c65d9678d4ce3c54b6 /arch/x86/dts | |
| parent | b5d54d26ea1354fede1121671a7ca3b9b44b5b5c (diff) | |
| parent | 95cfa1d46c61461bdadb195799a205b48b907a5e (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Corrected some FSP-M/FSP-S settings for Chromebook Coral
- ICH SPI driver and mrccache fixes for obtaining the SPI memory map
- Fixed various warnings generated by latest version IASL when compiling
ACPI tables
Diffstat (limited to 'arch/x86/dts')
| -rw-r--r-- | arch/x86/dts/chromebook_coral.dts | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index dea35b73a0..965d9f387d 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -516,6 +516,11 @@ 20 23 22 21 18 19 16 17 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ 25 28 30 31 26 27 24 29>; + + fspm,dimm0-spd-address = <0>; + fspm,dimm1-spd-address = <0>; + fspm,skip-cse-rbp = <1>; + fspm,enable-s3-heci2 = <0>; }; &fsp_s { @@ -594,13 +599,9 @@ fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>; fsps,emmc-rx-cmd-data-cntl2 = <0x10008>; - /* Enable Audio Clock and Power gating */ - fsps,hd-audio-clk-gate = <1>; - fsps,hd-audio-pwr-gate = <1>; - fsps,bios-cfg-lock-down = <1>; - - /* Enable lpss s0ix */ - fsps,lpss-s0ix-enable = <1>; + /* Enable WiFi */ + fsps,pcie-root-port-en = [01 00 00 00 00 00]; + fsps,pcie-rp-hot-plug = [00 00 00 00 00 00]; fsps,skip-mp-init = <1>; fsps,spi-eiss = <0>; |