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authorSimon Glass <sjg@chromium.org>2019-12-06 21:42:56 -0700
committerBin Meng <bmeng.cn@gmail.com>2019-12-15 11:44:26 +0800
commit5690d5c8f878846d862bd4a0256c2e8285413bff (patch)
treef68e617dae56d92fead2e272184f98101977aba4 /arch/x86/include/asm/arch-apollolake/iomap.h
parentbaaeb92c21370cc4717d4841906677f95ece55a3 (diff)
x86: apl: Add basic IO addresses
Add some fixed IO and mmap addresses for use in the device tree and with some early-init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/include/asm/arch-apollolake/iomap.h')
-rw-r--r--arch/x86/include/asm/arch-apollolake/iomap.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h
new file mode 100644
index 0000000000..4ce1017055
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/iomap.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ * Take from coreboot project file of the same name
+ */
+
+#ifndef _ASM_ARCH_IOMAP_H
+#define _ASM_ARCH_IOMAP_H
+
+#define R_ACPI_PM1_TMR 0x8
+
+/* Put p2sb at 0xd0000000 in TPL */
+#define IOMAP_P2SB_BAR 0xd0000000
+
+#define IOMAP_SPI_BASE 0xfe010000
+
+#define IOMAP_ACPI_BASE 0x400
+#define IOMAP_ACPI_SIZE 0x100
+
+/*
+ * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial
+ * node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE.
+ */
+#define PCH_DEV_UART PCI_BDF(0, 0x18, 2)
+
+#define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0)
+#define PCH_DEV_SPI PCI_BDF(0, 0x0d, 2)
+
+#endif