diff options
author | Simon Glass <sjg@chromium.org> | 2019-12-06 21:42:58 -0700 |
---|---|---|
committer | Bin Meng <bmeng.cn@gmail.com> | 2019-12-15 11:44:26 +0800 |
commit | 7656582378a3ff166080713d44cfc6fdc8cec6b0 (patch) | |
tree | c807bfc08a7c545d67cf621c5a685d047277f7db /arch/x86/include/asm/arch-apollolake | |
parent | 28eefefccfaa695fb44935ce8b04d50548d78b13 (diff) |
x86: apl: Add UART driver
Add a driver for the Apollo Lake UART. It uses the standard ns16550 device
but also sets up the input clock with LPSS and supports configuration via
of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/include/asm/arch-apollolake')
-rw-r--r-- | arch/x86/include/asm/arch-apollolake/uart.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-apollolake/uart.h b/arch/x86/include/asm/arch-apollolake/uart.h new file mode 100644 index 0000000000..d4fffe6525 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/uart.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _ASM_ARCH_UART_H +#define _ASM_ARCH_UART_H + +/** + * apl_uart_init() - Set up the APL UART device and clock + * + * This enables the PCI device, sets up the MMIO region and turns on the clock + * using LPSS. + * + * The UART won't actually work unless the GPIO settings are correct and the + * signals actually exit the SoC. See board_debug_uart_init() for that. + */ +int apl_uart_init(pci_dev_t bdf, ulong base); + +#endif |