diff options
| author | Simon Glass <sjg@chromium.org> | 2016-03-11 22:07:23 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 10:27:26 +0800 |
| commit | 08cb7420a2abe8fb0a99357f2a189c11bfc08d41 (patch) | |
| tree | 42b845e05e78529a60373971f66e8ccb376708b5 /arch/x86/include/asm/arch-broadwell | |
| parent | da3363d5d269d63747adbf7e067304206ae0d975 (diff) | |
x86: broadwell: Add an LPC driver
Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/include/asm/arch-broadwell')
| -rw-r--r-- | arch/x86/include/asm/arch-broadwell/lpc.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-broadwell/lpc.h b/arch/x86/include/asm/arch-broadwell/lpc.h new file mode 100644 index 0000000000..a718667400 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell/lpc.h @@ -0,0 +1,32 @@ +/* + * From coreboot soc/intel/broadwell/include/soc/lpc.h + * + * Copyright (C) 2016 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_LPC_H +#define _ASM_ARCH_LPC_H + +#define GEN_PMCON_1 0xa0 +#define SMI_LOCK (1 << 4) +#define GEN_PMCON_2 0xa2 +#define SYSTEM_RESET_STS (1 << 4) +#define THERMTRIP_STS (1 << 3) +#define SYSPWR_FLR (1 << 1) +#define PWROK_FLR (1 << 0) +#define GEN_PMCON_3 0xa4 +#define SUS_PWR_FLR (1 << 14) +#define GEN_RST_STS (1 << 9) +#define RTC_BATTERY_DEAD (1 << 2) +#define PWR_FLR (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) +#define GEN_PMCON_LOCK 0xa6 +#define SLP_STR_POL_LOCK (1 << 2) +#define ACPI_BASE_LOCK (1 << 1) +#define PMIR 0xac +#define PMIR_CF9LOCK (1 << 31) +#define PMIR_CF9GR (1 << 20) + +#endif |