diff options
| author | Eran Matityahu <eran.m@variscite.com> | 2017-12-14 20:20:02 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2018-01-03 14:01:38 +0100 |
| commit | af104ae5b87c8efb107ac282d09927d8346dc94f (patch) | |
| tree | db68d12e56ed3dc249d179941149d5ad9f76c8a1 /arch/x86/include/asm/byteorder.h | |
| parent | baefb63a13d106458577704ca4586b3f414c9520 (diff) | |
imx: spl: Fix NAND bootmode detection
commit 20f14714169 ("imx: spl: Update NAND bootmode detection bit")
broke the NAND bootmode detection by checking if
BOOT_CFG1[7:4] == 0x8 for NAND boot mode.
This commit essentially reverts it, while using the IMX6_BMODE_*
macros that were introduced since.
Tables 8-7 & 8-10 from IMX6DQRM say the NAND boot mode selection
is done when BOOT_CFG1[7] is 1, but BOOT_CFG1[6:4] is not
necessarily 0x0 in this case.
Actually, NAND boot mode is when 0x8 <= BOOT_CFG1[7:4] <= 0xf,
like it was in the code before.
Signed-off-by: Eran Matityahu <eran.m@variscite.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Diffstat (limited to 'arch/x86/include/asm/byteorder.h')
0 files changed, 0 insertions, 0 deletions