diff options
| author | Simon Glass <sjg@chromium.org> | 2016-03-11 22:07:26 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 10:27:26 +0800 |
| commit | 2627c7e2c100c702d540a277aa578176516d3a7c (patch) | |
| tree | e6a5fc89fc20ce379e15d3ed7f9f61d1b724f9cf /arch/x86/include/asm/global_data.h | |
| parent | 71a8f2080b77591eb14f61aba947aa9e869b847f (diff) | |
x86: broadwell: Add support for SDRAM setup
Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/include/asm/global_data.h')
| -rw-r--r-- | arch/x86/include/asm/global_data.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 0ca518ca38..3bc2ac24cf 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -19,6 +19,29 @@ enum pei_boot_mode_t { }; +struct dimm_info { + uint32_t dimm_size; + uint16_t ddr_type; + uint16_t ddr_frequency; + uint8_t rank_per_dimm; + uint8_t channel_num; + uint8_t dimm_num; + uint8_t bank_locator; + /* The 5th byte is '\0' for the end of string */ + uint8_t serial[5]; + /* The 19th byte is '\0' for the end of string */ + uint8_t module_part_number[19]; + uint16_t mod_id; + uint8_t mod_type; + uint8_t bus_width; +} __packed; + +struct pei_memory_info { + uint8_t dimm_cnt; + /* Maximum num of dimm is 8 */ + struct dimm_info dimm[8]; +} __packed; + struct memory_area { uint64_t start; uint64_t size; @@ -59,6 +82,7 @@ struct arch_global_data { enum pei_boot_mode_t pei_boot_mode; const struct pch_gpio_map *gpio_map; /* board GPIO map */ struct memory_info meminfo; /* Memory information */ + struct pei_memory_info pei_meminfo; /* PEI memory information */ #ifdef CONFIG_HAVE_FSP void *hob_list; /* FSP HOB list */ #endif |